Internal components: CPU, memory, input/output and buses

The components

• CPU (central processing unit): fetches, decodes and executes instructions.
• RAM (random-access memory): main memory holding the programs and data currently in use. It is read/write and volatile (contents are lost when power is off).
• ROM (read-only memory): non-volatile memory holding instructions needed at start-up, such as the bootstrap loader (firmware). Contents are not normally changed.
• Cache: a small amount of very fast memory, on or near the CPU, holding copies of frequently used instructions and data so the CPU waits less for RAM.
• Input/output (I/O) controllers: interfaces that let the CPU communicate with peripherals such as keyboards, displays and storage devices.

The buses

A bus is a set of parallel wires carrying signals between components.

• Address bus: carries the memory address (or I/O port) that the CPU wants to read from or write to. It is one way, from the CPU.
• Data bus: carries the data or instruction being transferred. It is two way (to and from the CPU).
• Control bus: carries control and timing signals such as memory read, memory write, clock, interrupt request and bus request. Lines go in both directions.

How much memory can be addressed?

Each wire on the address bus carries one bit. With n address lines the CPU can form 2ⁿ different addresses.

Addressable memory = 2ⁿ x (size of each memory location)

If memory is byte-addressable, each address holds one byte, so 2ⁿ bytes can be addressed. Widening the address bus by one line doubles the addressable memory. A wider data bus moves more bits per transfer (a larger word), which speeds up transfers but does not change how many locations exist.

Worked example

A CPU has a 24-bit address bus and memory is byte-addressable. How much memory can it address, in MiB?

1. Number of addresses = 2²⁴ = 16 777 216
2. Each address holds 1 byte, so 2²⁴ bytes.
3. 1 MiB = 2²⁰ bytes, so 2²⁴ / 2²⁰ = 2⁴ = 16 MiB

Answer: 16 MiB

Check yourself

1. A CPU has a 16-bit address bus. How many different memory addresses can it use?
   Show answer

   65536. 2¹⁶ = 65536.

2. A byte-addressable computer has a 20-bit address bus. How many KiB of memory can it address?
   Show answer

   1024 KiB. 2²⁰ bytes / 2¹⁰ = 2¹⁰ = 1024 KiB (which is 1 MiB).

3. An address bus has 12 lines and each memory location holds a 16-bit word. How many bytes can be addressed?
   Show answer

   8192 bytes. 2¹² = 4096 locations x 2 bytes = 8192 bytes.

4. A byte-addressable memory has 4 GiB of locations. How many address lines are needed?
   Show answer

   32. 4 GiB = 2² x 2³⁰ = 2³² bytes, so 32 lines.

5. Which bus carries signals in one direction only?
   • Data bus
   • Address bus
   • Control bus
   • Every bus carries signals in two directions
   Show answer

   Address bus. Only the CPU puts addresses on the address bus.

6. Why does a computer need ROM as well as RAM?
   • ROM is faster than cache
   • ROM can be written to more easily than RAM
   • ROM stores the files the user is editing
   • ROM keeps the start-up instructions when the power is off
   Show answer

   ROM keeps the start-up instructions when the power is off. RAM is volatile, so the instructions needed to start the computer must be in non-volatile ROM.

7. Which signal is sent along the control bus?
   • The address of the next instruction
   • Memory write
   • The instruction being fetched
   • The value in the accumulator
   Show answer

   Memory write. Read and write signals tell memory what to do; addresses go on the address bus and data on the data bus.

8. Explain why cache memory improves performance.
   Show answer

   Cache is very fast memory close to the CPU holding copies of frequently used instructions and data, so the CPU can get them without waiting for slower RAM.. Say what cache holds and why that reduces waiting.

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Sources

• Pearson Edexcel International Advanced Subsidiary/Advanced Level in Computer Science specification (2026)
• Pearson Edexcel IAL Computer Science IAS sample assessment materials (Unit 1, WCP01)

Last updated 8 November 2026. Spotted a mistake? Tell us.