The fetch-decode-execute cycle and register transfer notation

Fetch

1. The address in the PC is copied to the MAR.

2. The PC is incremented, so it points to the next instruction.

3. The CU sends a memory read signal on the control bus. The contents of the memory location whose address is on the address bus are sent along the data bus to the MBR.

4. The instruction is copied from the MBR to the CIR.

Decode and execute

• Decode: the CU splits the instruction in the CIR into its opcode (what to do) and operand (the data or the address to use), and works out what signals are needed.
• Execute: the instruction is carried out. A load puts an operand address in the MAR, sends a read signal and copies the value from MBR to ACC. A store places the address in the MAR and the data in the MBR, then sends a write signal. An arithmetic instruction uses the ALU, with the result in the ACC. A jump changes the PC.
• At the end of each cycle the CPU checks for interrupts, then the cycle repeats.

Register transfer notation

Register transfer notation (RTN) shows how data moves between registers. [X] means 'the contents of X' and ← means 'is copied into'.

Square brackets mean 'the contents of', so [[MAR]] means the contents of the memory location whose address is in the MAR. Steps 2 and 3 may happen at the same time.

Worked example

An instruction at address 140 is LOAD 145, which copies the value at address 145 into the accumulator. Show the transfers when the PC holds 140.

1. Fetch: MAR ← [PC], so MAR = 140; PC ← [PC] + 1, so PC = 141.
2. Memory read: MBR ← [[MAR]], so MBR = LOAD 145; CIR ← [MBR].
3. Decode: opcode LOAD, operand 145.
4. Execute: MAR ← 145 (the operand from the CIR); memory read; MBR ← [[MAR]]; ACC ← [MBR].

Answer: After the cycle the PC is 141, the CIR holds LOAD 145, and the ACC holds the value that was stored at address 145.

Check yourself

1. What is the first step of the fetch stage?
   • The contents of the MBR are copied to the CIR
   • The instruction is decoded
   • The PC is copied to the accumulator
   • The contents of the PC are copied to the MAR
   Show answer

   The contents of the PC are copied to the MAR. The address of the next instruction must be placed on the address bus first.

2. During a fetch the PC holds 120. What does the PC hold once the fetch stage is complete (one memory location per instruction)?
   Show answer

   121. PC ← [PC] + 1, so 121.

3. Which control signal is used when the CPU stores the accumulator's value into memory?
   • Memory read
   • Clock reset
   • Interrupt request
   • Memory write
   Show answer

   Memory write. Storing a value means writing to memory.

4. Which piece of register transfer notation means 'copy the instruction just read into the current instruction register'?
   • CIR ← [MBR]
   • MBR ← [CIR]
   • MAR ← [PC]
   • PC ← [PC] + 1
   Show answer

   CIR ← [MBR]. The instruction arrives in the MBR and is copied to the CIR.

5. Which component decodes the instruction?
   • Arithmetic logic unit
   • Memory address register
   • Control unit
   • Data bus
   Show answer

   Control unit. The CU interprets the opcode and generates control signals.

6. Explain how a jump (branch) instruction changes the flow of a program during the execute stage.
   Show answer

   The address in the operand is copied into the program counter, so the next fetch comes from that address instead of the next one in sequence.. A jump overwrites the PC; the next fetch uses the new address.

7. In the instruction ADD 45, what is 45?
   • The opcode
   • The clock speed
   • The operand
   • The status flag
   Show answer

   The operand. ADD is the opcode (what to do) and 45 is the operand (the data or address to use).

8. When a value is written to memory, which register holds the value just before the write signal is sent?
   • MAR
   • PC
   • CIR
   • MBR
   Show answer

   MBR. The MAR holds the address and the MBR holds the data to write.

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Sources

• Pearson Edexcel International Advanced Subsidiary/Advanced Level in Computer Science specification (2026)
• Pearson Edexcel IAL Computer Science IAS sample assessment materials (Unit 1, WCP01)

Last updated 8 November 2026. Spotted a mistake? Tell us.