ADC and DAC: sampling, quantisation and encoding

Sampling

The analogue signal is measured at regular time intervals. The sampling rate (samples per second, Hz) sets how often.

• Higher rate: the digital version follows the signal more closely, but more data is produced.
• Too low a rate misses changes. As a rule, sample at at least twice the highest frequency present in the signal.

Quantisation and encoding

Quantisation: each sample is rounded to the nearest of a fixed number of levels. With n bits there are 2ⁿ levels. The rounding difference is quantisation error; more bits means smaller steps and less error.

Encoding: each quantised level is written as an n-bit binary number and stored or sent to the processor.

Order matters in exam answers: sample, then quantise, then encode.

Step = range / (levels - 1)

Data size

Data produced = sampling rate x bits per sample x time (x number of channels).

Example: 1000 samples per second, 8 bits, 10 s gives 1000 x 8 x 10 = 80 000 bits = 10 000 bytes.

DAC

A digital-to-analogue converter turns each binary value into a matching voltage, producing a stepped signal that is usually smoothed. Uses: driving a speaker, setting a motor speed, dimming a light. In an embedded design: sensor -> ADC -> MCU -> DAC -> actuator.

Worked example

A weather station samples temperature 100 times per second with 12-bit resolution for 60 s. How many bytes are produced?

1. Bits = 100 x 12 x 60 = 72000
2. Bytes = 72000 / 8 = 9000

Answer: 9000 bytes

Check yourself

1. In what order does an ADC process an analogue signal?
   • Sampling, quantisation, encoding
   • Encoding, sampling, quantisation
   • Quantisation, encoding, sampling
   • Sampling, encoding, quantisation
   Show answer

   Sampling, quantisation, encoding. Measure, round to a level, then write the level as binary.

2. How many quantisation levels does a 10-bit ADC have?
   Show answer

   1024 levels. 2¹⁰ = 1024 levels.

3. A sensor is sampled 250 times per second at 8 bits per sample for 4 s. How many bytes of data are produced?
   Show answer

   1000 bytes. 250 x 8 x 4 = 8000 bits = 1000 bytes.

4. A 3-bit ADC covers 0 V to 7 V, with level 0 at 0 V and the top level at 7 V. What voltage step separates adjacent levels?
   Show answer

   1 V. 8 levels give 7 steps: 7 / 7 = 1 V.

5. In the same 3-bit, 0 V to 7 V ADC, a sample of 4.4 V is quantised to the nearest level. What denary level is stored?
   Show answer

   4. 4.4 V rounds to level 4 (binary 100).

6. What is quantisation error?
   • A sample taken at the wrong time
   • A bit flipped during transmission
   • A DAC producing too high a voltage
   • The difference between the true sample value and the level it is rounded to
   Show answer

   The difference between the true sample value and the level it is rounded to. Rounding to the nearest level loses detail; more bits reduce it.

7. What is the effect of increasing the sampling rate?
   • The number of quantisation levels increases
   • The digital data follows the signal more accurately, but the amount of data increases
   • The data size decreases
   • Quantisation error disappears
   Show answer

   The digital data follows the signal more accurately, but the amount of data increases. More samples per second means a closer match and more bits.

8. Which device would need a DAC?
   • A digital music player driving a speaker
   • A temperature sensor feeding a microcontroller
   • A keyboard sending key codes
   • A hard disk storing files
   Show answer

   A digital music player driving a speaker. The speaker needs a varying voltage made from stored digital samples.

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Sources

• Pearson Edexcel International Advanced Subsidiary and Advanced Level in Computer Science specification (2026), Issue 1
• Pearson Edexcel IAL Computer Science sample assessment materials (Unit 3 paper, resource booklet and mark scheme)

Last updated 8 November 2026. Spotted a mistake? Tell us.