Five-stage instruction pipelining

The five stages

Each instruction passes through five stages, one per clock cycle:

1. IF, instruction fetch: fetch the instruction from memory at the address in the program counter; increment the PC.

2. ID, instruction decode: decode the opcode and read the register operands.

3. EX, execute: the ALU performs the operation or calculates an address.

4. MEM, memory access: load from or store to data memory (if the instruction needs it).

5. WB, write-back: write the result into the destination register.

The pipeline idea

Without pipelining, instruction 2 starts only when instruction 1 has finished all five stages. With pipelining, as instruction 1 moves to ID, instruction 2 enters IF, and so on. Once the pipeline is full, one instruction completes every cycle.

For n instructions in a k-stage pipeline with no hazards: cycles = k + (n - 1). Without pipelining: k x n.

Pipelining improves throughput; it does not make any single instruction faster.

Three instructions finish in 5 + 2 = 7 cycles instead of 15

Branch hazards

A branch (jump) changes the program counter. The processor does not know whether the branch is taken, or where to, until the branch has been executed. Meanwhile, the pipeline has already fetched the instructions that follow it in memory.

If the branch is taken, those instructions are wrong: the pipeline is flushed (they are discarded) and fetching restarts at the branch target. The empty slots are called bubbles or stalls and waste cycles.

Ways to reduce the cost: branch prediction (guess the outcome, often from past behaviour), working out the target earlier, or filling the slot after a branch with a useful instruction.

Benefits and drawbacks

Benefits: higher throughput; every part of the processor is busy each cycle; no need for a faster clock.

Drawbacks: more complex control; hazards (branches, and an instruction needing the result of the one just before it) cause stalls and flushes; gains are lost in code with many branches; the speed-up is never quite k times because of the fill time and stalls.

Worked example

How many clock cycles do 6 instructions take in a five-stage pipeline with no hazards, and how many without pipelining?

1. Pipelined: the first instruction takes 5 cycles, then one more finishes every cycle.
2. Cycles = 5 + (6 - 1) = 10
3. Not pipelined: 5 x 6 = 30

Answer: 10 cycles pipelined against 30 cycles without.

Check yourself

1. Which is the correct order of the five pipeline stages?
   • ID, IF, EX, WB, MEM
   • IF, ID, EX, MEM, WB
   • IF, EX, ID, MEM, WB
   • MEM, IF, ID, EX, WB
   Show answer

   IF, ID, EX, MEM, WB. Fetch, decode, execute, memory access, write-back.

2. What happens in the WB stage?
   • The instruction is fetched from memory
   • The ALU carries out the operation
   • Data is loaded from data memory
   • The result is written into the destination register
   Show answer

   The result is written into the destination register. Write-back stores the result in a register.

3. How many clock cycles do 10 instructions take in a five-stage pipeline with no hazards?
   Show answer

   14 cycles. 5 cycles for the first, then one per instruction: 5 + 9 = 14.

4. How many clock cycles are saved by pipelining 20 instructions through five stages, compared with no pipelining?
   Show answer

   76 cycles. Without: 5 x 20 = 100. With: 5 + 19 = 24. Saving = 76.

5. In a five-stage pipeline, instruction A enters IF in cycle 1 and each later instruction enters one cycle after the previous. In which cycle is instruction D in its EX stage?
   Show answer

   6. D enters IF in cycle 4, ID in cycle 5, EX in cycle 6.

6. Why can a branch instruction cause a pipeline flush?
   • The branch instruction cannot be decoded
   • The ALU cannot compare two values
   • The instructions fetched after the branch may not be the next ones to execute, so they must be discarded
   • Branches are stored in data memory
   Show answer

   The instructions fetched after the branch may not be the next ones to execute, so they must be discarded. The outcome is known only at execution, after later instructions have entered the pipeline.

7. What is branch prediction?
   • Guessing the outcome of a branch so the pipeline can keep fetching from the likely next address
   • Removing every branch from a program
   • Running each path of a branch on a separate computer
   • Storing branches in the cache only
   Show answer

   Guessing the outcome of a branch so the pipeline can keep fetching from the likely next address. A good guess avoids most flushes; a wrong guess still needs a flush.

8. What does pipelining improve?
   • The time taken by one individual instruction
   • Throughput: the number of instructions completed per unit time
   • The clock speed
   • The size of main memory
   Show answer

   Throughput: the number of instructions completed per unit time. Each instruction still takes five stages; more of them finish per second.

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Sources

• Pearson Edexcel International Advanced Subsidiary and Advanced Level in Computer Science specification (2026), Issue 1
• Pearson Edexcel IAL Computer Science sample assessment materials (Unit 3 paper, resource booklet and mark scheme)

Last updated 8 November 2026. Spotted a mistake? Tell us.